Highly integrated power management applications often require the ability to measure voltage quantities that exceed the supply voltage in magnitude. This is primarily due to a basic need to maximize efficiency by running the power management IC with the lowest supply voltage possible, while still maintaining the ability to sample and measure quantities from the surroundings that could well exceed the battery voltage.
In today's highly integrated power management applications, a low power successive approximation register (SAR) analog-to-digital converter (ADC) is usually present to monitor on-chip and off-chip voltage quantities. The need often arises to extend the on-chip ADC range to sample voltage inputs that are greater than the power supply value. The ADC has to run on the lowest battery voltage possible while still maintaining the ability to sample inputs beyond the supply range.
The most widely used prior art bootstrap circuit in ADC applications is shown in FIG. 1. The circuit of FIG. 1 includes transistors MN1-MN10, MP1, and MP2; inverter INV; capacitors C1, C2, and C3; input node IN; output node OUT; clock signal nodes PHI and PHIZ; and source voltage Vdd. NMOS transistor MN1 connected to terminal OUT is the bootstrapped switch. A sampling capacitor (not shown) connects between terminal OUT and ground. This circuit is widely used in pipelined ADC converters to increase the bandwidth of the track and hold circuit at the front end of the converter. Most pipelined ADC converters typically have relatively small fully differential ranges that fall well within the supply range of the chip. As a result, the prior art switch presented in FIG. 1 will do the job just fine.
The circuit of FIG. 1 operates as follows. First consider the charge pump formed by transistors MN8, MN9, capacitors C1 and C2, and the inverter INV. It works as follows, assume that initially the voltage across the capacitors C1 and C2 is zero, when the clock signal PHIZ goes high, the top plate of capacitor C1 goes to supply voltage VDD and since the bottom plates of capacitors C2 and C3 are grounded for this state, those capacitors are charged till their top plates reach voltage VDD−VTN (where VTN is the threshold voltage for NMOS transistors MN9 and MN10). When the clock signal PHIZ goes low, the top plate of capacitor C2 is pushed well above voltage VDD (or 2VDD−VTN to be exact) yielding complete charging of capacitor C1 to VDD through the switch MN8. With the next phase when PHIZ goes high again, since capacitor C1 is charged to VDD, the top plate of capacitor C1 will be pushed to 2 VDD (two times voltage VDD) and capacitors C2 and C3 will be completely charged to VDD. In steady state, capacitors C1, C2, and C3 will charged to VDD and the voltage on the top plates of capacitors C1 and C2 will change between VDD and 2 VDD. The classical bootstrapped switch reaches its steady state after at least one clock period.
Under the assumption that all the capacitors are charged to VDD, the bootstrapped switch operates as follows: when PHIZ goes high, the bottom plate of capacitor C3 is grounded and switch MN10 is on, hence capacitor C3 is charged to VDD; switch MP2 is also on, driving the gate of transistor MP1 to VDD, hence transistor MP1 is off and finally transistor MN6 is on and grounds the gate terminal of the main switch MN1. Since their gate terminal is grounded, transistors MN3, MN2, and MN1 are off. During this phase, the switch MN1 disconnects the input node IN from the output node OUT and capacitor C3 is charged to VDD. When PHIZ goes low, since transistor MN6 is off, the gate terminal of MN1 becomes high impedance. Initially, the bottom plate of capacitor C3 is floating, but because of the fact that switch MN4 connects capacitor C3 between the gate and source terminal of transistor MP1, this transistor turns on immediately and the charge stored on capacitor C3 starts flowing to the gate terminal of main switch MN1. While the gate voltage of switch MN1 rises, transistor MN2 turns on and forces the bottom plate of capacitor C3 towards the input voltage VIN, which pushes the top plate of capacitor C3 to voltage VDD+VIN. Eventually this voltage appears at the gate of transistor MN1 and as a result transistor MN1 turns on completely to connect the input terminal IN to the output terminal OUT. Transistor MN2 turns on completely to connect input terminal IN to the bottom terminal capacitor C3 and transistor MN3 turns on completely to drive the gate of transistor MP1 to the input voltage level. The gate-to-source voltages of all these four switches MN1, MN2, MN3 and MP1, are all equal to VDD. An important detail about device reliability is the following: even though the bootstrapped switch can be turned on by pulling the gate terminal of MP1 to ground, if the input signal is equal to VDD then the voltage difference between the gate and source of transistor MP1 would be 2VDD. For this reason, during this phase the bootstrapped switch MN1 is turned on, the gate voltage on transistor MP1 is forced to the input signal through the switch MN3 so that the gate-to-source voltage of transistor MP1 is bounded within VDD, and hence the reliability is enhanced. The main challenge of this switch is the design of the scheme that protects MP1 by restricting maximum voltage appearing across its terminals.
Even though the prior art switch in FIG. 1 performs well for input signal levels that are within the supply range, it is useless when the input signal exceeds the supply voltage. The reason is the following: When the switch is turned on, input voltage appears at the gate of transistor MP1. As mentioned previously, this is necessary in order to restrict the gate-to-source voltage of this device to VDD. Since switch MP2 is a PMOS transistor, if its drain voltage exceeds the supply voltage (because the input signal is greater than VDD), the parasitic drain-substrate diode of this device will be forward biased, which will yield a huge current flow through the path formed by transistors MN2 and MN3, and the parasitic body diode of transistor MP2. This current path renders the prior art bootstrapped switch useless for applications where input signal level exceeds supply voltage. The body diode that would be activated here is that between the drain D of transistor MP2 and the bulk B of transistor MP2, shown in FIG. 2. A cross-section of transistor MP2, shown in FIG. 2, includes p type region p; n type region n; drain D; gate G; source S; and bulk B.